SF32LB55x Hardware Design Guide — Schematic Design Guidelines¶

5. Schematic Design Guidelines¶

5.1. Power System¶

SF32LB551 in QFN68L has no VDD2, BUCK2_VSW, BUCK2_VOUT, LDOVCC2_VOUT, or AVDD_DSI pins. Apply the supply and capacitor tables only to pins present on the selected package. BGA packages provide two BUCK outputs; BUCK2 supports BUCK or LDO operation, with BUCK mode recommended. QFN68L provides one BUCK output.

Place the required capacitors close to the corresponding pins, keep BUCK current loops compact, and verify the BUCK/LDO operating mode before layout. The reset circuit and POR/BOR timing should be checked on actual hardware.

The source documents disagree: Table 3-3 of SiFli's Chinese hardware application guide and item 9 of the V1.0 schematic checklist specify 1 µF for VDD_RTC, while C0313 in the guide's reference schematic is labeled 0.1 µF. They do not explain when each value applies. Confirm the required value with SiFli for the exact device before design release; do not resolve the discrepancy by assumption.

Power VDD1 and VDD2 simultaneously; SF32LB551 has no VDD2. Pull RSTN up to the VDD1 input-voltage domain and connect 0.1 µF to ground. The reference drawing labels the pull-up rail 1.8 V/3.3 V and uses a 10 kΩ resistor; use the level corresponding to the selected design's VDD1 domain. Figure 5.1-1 shows a 1.50 V POR level, configurable BOR from 2.5 V to 1.5 V, and a 0.7 V RSTN marker. The measured trace in Figure 5.1-3 illustrates about 700 µs from the supply rise to reset release in that example; it is not a guaranteed reset delay for every design.

Select a 4.7 µH BUCK inductor with DCR ≤ 0.4 ohm and saturation current Isat ≥ 450 mA, as specified in SiFli's hardware application note.

5.2. Boot Mode¶

High mode enters download mode after power-on; low mode boots the user program. Ensure production fixtures can force the required boot state and that boot-related pins are not blocked by product enclosure or test access limitations.

The Mode pin shares the VDDIOA voltage domain. Use an external 10 kΩ resistor to hold it at the required supply or ground level; do not leave it floating or allow unintended toggling. Production boards must expose a Mode test point for firmware download and crystal calibration; a jumper is not required. On test boards, reserve a jumper so a stalled application can be recovered by booting into download mode.

5.3. Clock Generation¶

Place both crystals close to the chip, keep traces short and symmetric, reserve matching capacitor footprints, and protect crystal nets from RF, BUCK, display, and motor noise.

5.4. RF¶

The SF32LB55x RF front end uses on-chip wideband matching-filter technology. Keep the RF PCB trace at 50 ohms characteristic impedance, reserve a π-type matching network for spurious filtering and antenna matching, and determine final component values by testing the actual antenna and PCB layout. If the selected antenna is already matched, no additional RF components are normally required beyond the reserved network.

Keep RF routing on a continuous reference ground, place the matching circuit close to the chip side, keep AVDD_BRF filtering close to the pin, and keep DC-DC, VBAT, crystal, high-speed clock, SPI, SDIO, I2S, and UART traces away from the RF area.

The RF reference circuit places C0323 (15 pF/50 V) in series with ANT and leaves the two shunt positions C0318 and C0319 unpopulated (NF). These are example values, not universal antenna-matching values.

5.5. Storage Interfaces¶

SF32LB55x supports OPI PSRAM, QSPI NOR/NAND Flash and PSRAM, and SDIO eMMC or Micro SD options. Package selection affects which pins and interfaces are available, so storage selection should be completed before pin locking and PCB stack-up review.

BGA145 has one external OPI-PSRAM channel; BGA169 has two. Tables 5.5-1 to 5.5-3 describe the BGA145 configuration and the two BGA169 memory devices, not three channels on one package. The QSPI tables correspond to QSPI2, QSPI3, and QSPI4. The SDIO tables cover SDIO1 in 4-bit/8-bit modes and SDIO2 in 4-bit mode.

Prefer QSPI2 for external QSPI PSRAM. If HCPU GPIO controls an external OPI/QSPI PSRAM supply, use a PU-type HCPU pin with High enabling and Low disabling power. If switching VDD_SIP for internal Flash, use PA58 with the same High-on/Low-off polarity. Ask SiFli's FAE to assess Flash space for LCPU accelerometer and heart-rate algorithms before deciding whether to add QSPI4 NOR Flash.

The source tables use inconsistent direction labels. In the BGA145 reference schematic and the BGA169 device 1 and device 2 reference schematics, MCU pins PA37/PA20 and PA07/PA08, respectively, drive the external PSRAM's CS# and CLK pins. The tables below therefore describe CS# and CLK from the MCU side: MCU output, PSRAM input. The schematics do not establish a fixed direction for DQS/DM; verify its function and direction in the selected PSRAM datasheet.

Each illustrated PSRAM uses a 1.8 V supply, three 0.1 µF capacitors and one 1 µF/6.3 V capacitor. RESET# and NC/CLK# connections shown unconnected belong to the depicted memory part; check the selected part's datasheet rather than generalizing them.

5.6. Display and Touch Interfaces¶

Display choices include MIPI DSI, SPI/QSPI, MCU8080, and JDI. Choose the panel before pin assignment and PCB routing so the interface width, clocking, power control, touch interrupt, and backlight strategy are reviewed together.

Both parallel and serial JDI are supported through the PA-side LCDC1 or PB-side LCDC2 multiplexed signal groups. The tables below list only the PA/LCDC1 assignments; SiFli recommends the PB/LCDC2 interface. The source guide does not provide a pin-by-pin LCDC2 table, so confirm the actual assignment against the chip pin-mux documentation rather than inferring it from the LCDC1 tables.

Display pin-selection notes:

• TE may use another GPIO in the PA group.
• If the panel supports TE over DSI, a separate TE pin is not required.
• RESET may use another GPIO in the PB group.

Display pin-selection notes:

• TE may use PA77 or another PA-group GPIO configured to emulate the signal.
• RESET may use any GPIO. For an always-on display (AOD), SiFli recommends a GPIO in the PB group.

Display pin-selection notes:

• TE may use PA77 or another PA-group GPIO configured to emulate the signal.
• RESET may use any GPIO. For an always-on display (AOD), SiFli recommends a GPIO in the PB group.

The SiFli hardware application guide labels RDX as a read strobe but ends its description with “to write data.” That phrase conflicts with the RDX label and the paired WRX write-strobe signal, so it is treated here as a source wording error. Readback support and timing depend on the selected display controller; verify them against that controller's datasheet.

For BL_PWM, use a GPIO with the GPTIM1_CHx function and configure an appropriate pull-up or pull-down state to prevent the backlight from turning on unexpectedly during cold start.

5.7. Wake, GPADC, and Manufacturing Interfaces¶

Wake, analog, debug, and production access must be planned with the enclosure and fixture in mind. Wake pins need defined idle levels and ESD protection, GPADC dividers must balance settling time and leakage, and debug/download access must remain reachable in EVT and production.

SF32LB55x provides four HCPU wake sources (WKUP_A0–WKUP_A3) and six LCPU wake sources (WKUP_B0–WKUP_B5). Each wakes its associated CPU; only the six LCPU sources wake the system from Hibernate. None of these ten inputs may float: add external pull-up or pull-down resistors to suit the function and avoid sleep leakage.

In the reference circuit, KEY1 connects to PB48 with a 10 kΩ pull-up to VDD_1V8, ESD protection, and a capacitor. The KEY2 network shows 10 kΩ pull-ups, ESD protection, and jumper-selectable connections to PA08, PA77, and PA78; C0004 is marked NF. These are circuit examples, not a list of wake-capable pins: PA08 is not listed in Table 5.7-1. Choose the actual wake-capable input from that table and keep every input at a defined idle level.

Use a GPIO with GPTIM1_CHx for motor PWM. Select the appropriate PU/PD pin behavior so a cold start cannot unintentionally activate the motor. The reference circuit uses GPIO17 (PA44), a low-side transistor and a 1 MΩ gate pull-down, with a 3 V motor supply and a separate 3.3 V MCU supply.

SiFli's hardware application guide describes a five-channel, 10-bit GPADC with an input range of 0–0.9 V. For a conservative board design, connect VIN directly only when it is below 0.9 V; divide higher voltages so VADC stays below 0.9 V. For battery sensing, the source suggests R1:R2 near 5:1 and MΩ-range resistors: lower divider current comes at the cost of longer settling. The illustrated divider adds 0.1 µF from VADC to ground. Use VADC = VIN × R2 / (R1 + R2) and check the maximum battery voltage and resistor tolerances; Table 5.7-2's current values are for VIN = 4.2 V, not every battery condition.

Source discrepancy: the higher-priority OpenSiFli hardware application guide describes a five-channel, 10-bit GPADC with a 0–0.9 V input range. Item 2 of the V1.0 schematic checklist sets a 1.0 V maximum but does not specify the channel count. In contrast, the SF32LB55x datasheet V1.7.2, section 3.2.1 specifies eight single-ended inputs or four differential pairs, with a 0–1.1 V single-ended range and a −0.7 to 0.7 V differential range; its pin table lists GPADC_CH0–CH7. The current SDK ADC guide also maps eight channels (0–7) and lists 1.1 V as the maximum sampled voltage. SiFli has not explained the conflicting channel counts and voltage limits. This guide therefore retains the higher-priority hardware application's five-channel and 0–0.9 V design basis pending written clarification. Keep VADC below 0.9 V; do not treat 1.0 V or 1.1 V as an approved design limit, and confirm channel availability for the selected device and package.

Route heart-rate and accelerometer I2C/SPI, control and wake-interrupt interfaces through LCPU. Select low-Iq DC-DC converters, LDOs or load switches so sensor supplies can be switched as needed.

External Bluetooth audio communicates through HCPU UART1. Match voltage levels or add a level translator; when cutting module power, shut down the translator supply simultaneously to avoid leakage. If the audio module stays powered while SF32LB55x enters Standby and its supply enable is active-low, use an LCPU GPIO with default PD behavior.

Do not leave UART RXD floating; enable its internal pull-up during firmware initialization. UART3 is the default log port. SiFli provides an offline programmer for production flashing and crystal calibration. Reserve at least VBAT, GND, VDDIOA, VDDIOB, RSTN, Mode, SWDIO, SWCLK, RXD1, TXD1, RXD3 and TXD3 test points. The production fixture subset is VBAT, GND, boot_mode, VDDIOB, RXD3 and TXD3. VBAT and boot_mode are source fixture labels; map them to the actual board supply and Mode connection before wiring.

The source drawing connects VDD_1V8 to connector pin 1 (VTref), SWDIO to pin 7, and SWCLK to pin 9 through 22 Ω series resistors. Standard J-Link SWD also uses pin 1 for VTref, the target-voltage reference input, not a probe power output. Verify the header orientation and 1.8 V compatibility before connecting a standard cable.

Last updated: 2026-10-21