SF32LB55x¶

Overview¶

The SF32LB55x series is a mainstream, ultra-low-power AIoT microcontroller family for BLE-connected products that need stronger display capabilities, more memory headroom, and a wider choice of packages than entry-level Bluetooth MCUs.

Its big.LITTLE dual-core architecture pairs two Arm Cortex-M33 STAR-MC1¹ processors: a high-performance application core running at up to 240 MHz and an ultra-low-power core running at up to 48 MHz. This lets a product keep demanding UI work on the application core while assigning sensor processing, standby control, and BLE tasks that must remain active to the low-power core.

SiFli's official product brief and datasheet list BLE 5.2, the ePicasso 2.5D graphics engine, dual LCD controllers, a TinyML-oriented neural-network matrix accelerator, and 1,312 KB of on-chip SRAM (1,088 KB HCPU + 224 KB LCPU), along with support for external NOR, NAND, eMMC, and PSRAM. This makes SF32LB55x a practical choice for wearables, sensor-rich products, and compact HMI designs that need more resources than SF32LB52x but do not require a higher-tier 56/58-family device.

SiFli's chip model guide notes that SF32LB55x was defined before the later 52/56/58 families, so its suffixes do not fully follow the newer numbering convention. Use the complete orderable part number and package-specific capability tables when selecting a device; do not infer every capability from the suffix alone.

Applications¶

SF32LB55x is recommended for BLE-first products that need a stronger UI, larger working memory, or more flexible packaging than entry-level wearable MCUs, including:

• Smartwatches and fitness bands
• Health-monitoring wearables
• Smart locks and smart-home controllers
• Sensor-rich connected accessories
• Compact graphical HMI products
• Smart stylus and pen-computing accessories
• Portable terminals and handheld controllers

Choose SF32LB55x when the design needs one or more of these capabilities:

• BLE 5.2 connectivity with very low receive current
• MIPI DSI command-mode display support
• Larger SRAM for LVGL, graphics assets, sensing, or TinyML workloads
• A user-programmable low-power processor
• More GPIO or denser package options than SF32LB52x
• External NOR, NAND, eMMC, QSPI-PSRAM, or OPI-PSRAM flexibility

Development Resources¶

Features and Specs¶

Compute and Memory¶

• High-performance Arm Cortex-M33 STAR-MC1 application processor, up to 240MHz
• Ultra-low-power Arm Cortex-M33 STAR-MC1 processor, up to 48MHz
• Up to 360 DMIPS / 965 EEMBC CoreMark on the application processor
• Up to 72 DMIPS / 193 EEMBC CoreMark on the low-power processor
• 1,088 KB application SRAM, including 64 KB retention SRAM
• 224 KB low-power SRAM, all retention SRAM
• External memory interfaces for NOR, NAND, eMMC, QSPI-PSRAM, and OPI-PSRAM

Graphics, Display, and AI¶

• ePicasso 2.5D graphics engine with hardware rotation, scaling, mirroring, and alpha blending
• eZip losslessly decompresses graphics and can be chained with ePicasso
• The ePicasso transform layer supports resolutions up to 640 × 640; generic layers and display output support up to 1024 × 1024, and display output reaches up to 60 fps
• LCD controller supports 8080, SPI, Dual-SPI, Quad-SPI, DPI, MIPI DSI, and JDI reflective-display interfaces on supported variants; verify availability for the selected model
• TurboPixel framebuffer compression lets the LCD controller read compressed frame data and decompress it for display, reducing framebuffer storage and read-bandwidth requirements
• Dual LCD controllers; always-on-display interfaces and dual-display capability depend on the selected model and package
• Neural-network matrix accelerator for TinyML workloads, up to 1.92 GOPS and 5.73 TOPS/W

Wireless Connectivity¶

• Bluetooth Low Energy 5.2
• BLE 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps modes
• Sensitivity down to -100 dBm in 1 Mbps mode
• Maximum transmit power: 10 dBm
• Receive peak current: 2.0 mA at 3.3 V

Security¶

• AES and CRC hardware accelerators
• True random number generator (TRNG)
• PSA Certified Level 1

Peripherals and I/Os¶

• Up to 5 UART, 6 I2C, and 4 SPI interfaces across the family; counts vary by model, as shown below
• I2S and PDM interface counts vary by model (see the table). Each PDM interface can connect up to two digital microphones, so interface count is not microphone count; also check pin availability for the selected model.

SS6600A8 source note: The current SiFli Chip Model Guide lists this part's package, co-packaged memory, GPIO, and display interface, but does not specify its per-model UART, I2C, SPI, I2S, PDM, or Sigma-Delta ADC counts. Table 0-1 of the DS5501 V1.7.2 datasheet also has no separate row for SS6600A8. Its counts are therefore marked “Not specified”; do not infer them from SF32LB551U4O5 just because both use QFN68L. Confirm the configuration with SiFli before pin assignment.

• 1 × USB 2.0 FS host/device interface
• 1 × 10-bit GPADC (SAR ADC): the datasheet specifies up to 8 single-ended inputs or 4 differential pairs, with a 0–1.1 V single-ended input range
• ADC source discrepancy: The DS5501 V1.7.2 datasheet specifies up to 8 single-ended inputs or 4 differential pairs and a 0–1.1 V single-ended range. The SF32LB55x hardware application note states 5 channels and a 0–0.9 V input range. Confirm the channel mapping and limits for the exact part and SDK revision before designing the analog front end.
• 16-bit Sigma-Delta ADC with 5 channels on the BGA145 and BGA169 models shown above; it is not present on the QFN68L models
• Temperature sensor
• 2 × low-power voltage comparators
• Peripheral Task Controller (PTC)
• GPIO count varies by package; see the package table and source-discrepancy note below

Power Supply and Package¶

• Power supply range is variant-specific: 2.97 V to 3.63 V for SS6600A8; 1.71 V to 3.63 V for 551U4O5 and the selected BGA variants
• Operating temperature is variant-specific: -20 °C to +70 °C for the documented QFN variants; -40 °C to +85 °C for the selected BGA variants
• Integrated power management with two high-efficiency buck regulators and low-power LDO
• Sleep current with RTC wake-up: 600 nA
• Sleep current with pin wake-up: 280 nA
• Package options: QFN68L, BGA145, and BGA169

Family Variants¶

SF32LB55x devices are offered in QFN and BGA packages. Select the package early because GPIO count, integrated memory, display-interface choice, and PCB process all vary materially by package.

Package choice is not just a layout decision here. SiFli's chip model guide explicitly notes that the 55x family supports all or only part of the display-interface set depending on package, so package selection should be locked before display, memory, and pin-budget planning are finalized. Parts in the same package are pin-to-pin compatible; confirm the exact memory configuration and display requirements before choosing a compatible replacement.

The following current models listed in SiFli's chip model guide make the package and memory trade-off explicit. The part-number suffixes in this older family do not consistently follow SiFli's newer naming convention, so use the full orderable part number rather than decoding the suffix by rule.

For SF32LB557VD3A6, the current SiFli Chip Model Guide and Table 0-1 in the DS5501 V1.7.2 datasheet list 71 HCPU + 42 LCPU = 113 GPIOs. The datasheet's feature and package summaries, as well as the PB0001 V1.3 Product Brief, instead give BGA169 119 GPIOs (71 HCPU + 48 LCPU). The official sources therefore conflict, including within the datasheet. This page follows the model-specific row and current model guide (113). Before assigning pins or finalizing the design, verify GPIO availability against the selected package's ball map and confirm the orderable part with SiFli. Also verify the variant's supply and temperature ratings, full part number, and integrated-memory configuration against the DS5501 V1.7.2 datasheet, PB0001 V1.3 Product Brief, and SiFli Chip Model Guide. The BGA145 and BGA169 packages measure 7 × 7 × 0.94 mm with 0.5 mm pitch.

Integration Path¶

Use this sequence to turn an SF32LB55x shortlist into a validated design:

1. Prove the firmware path. Start with the SiFli SDK getting-started guide, then use the SiFli SDK workflow and examples to validate the required display, Bluetooth, and low-power behavior.
2. Plan the evaluation hardware. μForge does not currently catalogue an SF32LB55-specific module or development board. Use the SF32 Product Selector to select the closest available evaluation platform, then verify package and interface coverage before transferring results to a 55x design.
3. Design and review the hardware. Before releasing the schematic or layout, use the μForge hardware design guide, including its schematic and PCB-layout checklists.
4. Verify the authoritative source. Confirm the exact orderable part and package against the SiFli datasheet, user manual, original design guide, and hardware application note source.

Frequently Asked Questions¶

What are the key specifications of SF32LB55x? SF32LB55x pairs an application CPU (Cortex-M33 @240 MHz) with a low-power core (Cortex-M33 @48 MHz, a user-programmable core), 1,312 KB of internal SRAM and Bluetooth Low Energy (BLE) only. Graphics: ePicasso 1.0. Package: QFN68 / BGA145 / BGA169 (7 × 7 mm (QFN68)). USB 2.0 FS. Family-level values; verify the exact part number's datasheet.

Which display interfaces does SF32LB55x support? SPI / DSPI / QSPI / 8080 / JDI / RGB / MIPI. Availability varies by part number and package.

How much in-package memory does SF32LB55x offer? Up to 16 MB + 2 MB of in-package PSRAM and up to 8 MB of in-package NOR Flash, depending on the part number.

What supply voltage does SF32LB55x need? 1.71–3.63 V, depending on the variant. Confirm the exact range in the datasheet.

Where do I start a hardware design with SF32LB55x? Start with the SF32LB55x hardware design guide for schematic, power, clock/RF and PCB layout guidance, then use the schematic and layout checklists before releasing the board.

Related Products¶

Development Kits¶

Use the official hardware application note, reference schematics, and checklist as the starting point for package selection, power-tree definition, display-interface choice, memory planning, RF layout, and production-test planning.

Reference Products¶

Typical SF32LB55x end products include smartwatches, fitness bands, health-monitoring wearables, smart locks, connected accessories, smart-home controllers, and compact graphical HMIs.

Last updated: 2026-10-21