SF32LB57x Hardware Design Guide — Design Review Checklist and References¶

This page covers Sections 7-10: the customer design self-check, related documents and references, appendices, and revision history. Return to the PCB layout guidelines.

7. Customer Design Self-Check¶

Complete this checklist before requesting a schematic review, PCB layout review, or EVT release. The customer-side design owner should record the result and evidence for each item and, where applicable, cite schematic pages and attach PCB screenshots, measurements, or review records.

7.1. Package and Part Number¶

• Orderable part number, power family, package, and pinout are confirmed.
• The schematic-library symbol and PCB footprint match the datasheet.
• QFN/BGA pads, stencil, exposed pad, and via design are reviewed.

7.2. Power¶

• Every supply pin stays within its specified voltage and load limits; capacitor values and placement meet the datasheet requirements.
• BUCK inductor, capacitors, and feedback routing meet layout requirements.
• Internal LDO outputs are not misused as high-current peripheral supplies.
• Power paths match the selected supply family; verify the applicable charger/OVP, VBUS, VBAT, VCC, and/or PVDD connections against the exact package-and-variant power table, without mixing the battery-powered and 3.3 V supply topologies.
• Peripheral power rails can be switched off and default to safe states.

7.3. Clocks¶

• 48 MHz and 32.768 kHz crystals meet recommended parameters.
• Crystals are placed close to the chip, with keep-out areas defined around them.
• Crystal routing is away from power, RF, USB, SDIO, display, and charging noise.

7.4. Storage and Boot¶

• If the selected part includes co-packaged memory, its configuration and effect on available external memory interfaces and package pins are confirmed for that exact package and variant.
• External boot media type, pull-ups, power control, and default state are correct.
• Boot configuration and download/debug test points are reserved.

7.5. RF¶

• The antenna feed trace is designed for a controlled 50 Ω impedance.
• π matching network is placed near the chip.
• RF trace has a continuous reference ground and via shielding.
• RF is isolated from noise sources and high-speed interfaces.

7.6. Display and Touch¶

• Display interface, resolution, and pin group meet panel requirements.
• Display, backlight, and touch supplies are controllable.
• Touch interrupt uses a wake-capable GPIO if wake is required.
• FPC and high-speed display traces are kept away from RF.

7.7. Audio and Analog¶

• MIC_BIAS, AUD_VREF, and AVDD33_AUD decoupling is correct.
• Analog input DC-blocking and filtering are correct.
• DACP/DACN differential routing and matching network are correct.
• GPADC input voltage, divider, filtering, and shielding are correct.

7.8. General Interfaces¶

• UART, I2C, SPI, SDIO, USB, and CAN wiring and IO levels are correct.
• The I2C pull-up rail switches with the corresponding peripheral I/O supply to prevent leakage when that domain is off.
• USB ESD, 90 ohm differential routing, and VBUS wake detection are implemented as needed.
• External wake signals use wake-capable pins.

7.9. Production and Reliability¶

• DBG-UART, SWD, boot-mode, PA00, PA01, PA34, power, and ground test points are reserved.
• Test points meet fixture probe requirements.
• ESD, EOS, OVP, reverse-protection, and surge strategy are reviewed.
• Production firmware download, crystal calibration, and RF test flow are executable.

7.10. Design Review Release Criteria¶

Before design freeze, use these release criteria:

• Every applicable item is closed with evidence such as schematic page references, PCB screenshots, measurements, or review notes; each item marked not applicable has a rationale.
• Every deviation from the datasheet or reference design has a project-level design reason.
• RF, crystals, charging, power, USB, display, audio, and production test points have been reviewed by the responsible owners.
• The low-power current budget includes all peripheral standby currents, pull-up currents, and regulator Iq.
• EVT bring-up paths for download, logs, current measurement, reset, and boot control are accessible.

8. Related Documents and References¶

Use the latest official documents to verify electrical limits, package data, pin multiplexing, software configuration, component qualification, and manufacturing constraints.

The Schematic Checklist (Section 5.8) and PCB Layout Checklist (Section 6.10) reproduce SiFli's official SF32LB57x design self-check tables item by item, alongside the schematic and PCB layout guidance they check against.

9. Appendices¶

The appendices collect application and reference-design context. Use them after the main schematic and PCB rules in Sections 5 and 6 have been applied.

9.1. Appendix A. A Typical SF32LB57x Product¶

A typical SF32LB57x product may include the MCU, power tree, 48 MHz and 32.768 kHz crystals, RF matching and antenna, display and touch controller, boot storage, audio input/output, sensors, an optional camera, and whichever USB/SDIO/CAN/UART/I2C/SPI peripherals the product needs, together with debug and production-test access. Review charging, OVP, load-switch selection, and low-power leakage where applicable to the chosen power architecture.

10. Revision History¶

10.1. Checklist Revision History¶

The item-by-item checklist in the Schematic Checklist and PCB Layout Checklist is versioned separately from the guide, following the design self-check tables in SiFli's SF32LB57x hardware application note.

Last updated: 2026-10-10