SF32LB52x Hardware Design Guide — Storage & Manufacturing¶

5.6. Storage and Connectivity¶

5.6.1. Storage¶

Quick Summary

• External boot options include SPI NOR, SPI NAND, and SD NAND; eMMC is available on supported externally regulated variants.
• Bootstrap pins PA13 and PA17 select the boot medium.
• The application notes and schematic-design guide specify PA21 for boot-storage power switching, whereas the official checklist specifies PA11 for external Flash on battery-powered variants. Confirm the applicable control pin with SiFli for the exact design. Separately, PA21 must power-cycle MPI-attached NOR Flash of 32 MB or larger so ROM can recognize it after reset or Hibernate entry; during Hibernate, VDD_SIP must be off to avoid leakage through co-packaged-memory I/O.

Design Goal

Choose a boot medium and storage power architecture that support firmware size, update strategy, low-power states, and reliable ROM boot after reset or Hibernate.

5.6.1.1. Storage Interface Description¶

The chip supports external SPI NOR Flash, SPI NAND Flash, and SD NAND Flash. eMMC is supported only on the 52B/D/E/G/J regular-powered variant.

5.6.1.2. Boot Configuration¶

5.6.1.3. Boot Storage Power Control¶

The higher-priority OpenSiFli application guides and schematic-design guide specify PA21 for boot-storage power switching, active high (on) and low (off); use PA21 as the source-supported design basis. The checklist workbook linked from the SiFli Wiki instead lists PA11 for external-Flash switching on battery-powered variants. Do not substitute PA11 based only on that workbook. It does not say whether PA11 is a separate board-level enable or a pin-assignment conflict, so confirm the exact net and variant with SiFli before release.

Common Mistakes - Storage

• Missing bootstrap resistors or populating them for the wrong boot medium.
• Leaving the source-confirmed boot-storage power-switch control disconnected.
• Treating eMMC as available on all variants.
• Keeping large NOR Flash always powered when 4-byte mode can break ROM recognition after restart.

Storage Checklist

• Boot medium is selected and documented before PCB layout.
• PA13/PA17 bootstrap pull options match the boot table.
• The source-confirmed, variant-specific pin controls all required boot-storage power switches; the PA11/PA21 discrepancy has been resolved with SiFli.
• eMMC VCC/VCCQ tradeoff is reviewed for regular-powered designs.
• Bring-up plan covers boot-mode strapping, storage rail timing, ID read, and firmware download.

5.6.2. Sensors¶

Quick Summary

• Sensors typically connect through I2C or SPI. Power-gate unused sensors to reduce standby current; keep sensors needed for wake-up in the required operating mode.
• Wake-capable sensor interrupts must be assigned before pinout freeze.

Design Goal

Keep sensor power, interrupt, and bus routing reliable while allowing unused sensors to shut down cleanly in low-power modes.

The SF32LB52x can connect to heart-rate, accelerometer, geomagnetic, and similar sensors. Choose a load switch with low Iq for sensor power switching.

Sensor Checklist

• Sensor bus, interrupt, reset, and power-enable pins are assigned.
• The sensor load switch's quiescent current (Iq) and shutdown current meet the standby target.
• Pull-ups are placed on the correct sensor I/O voltage rail.
• Bring-up plan covers bus scan, interrupt wake, and sensor power cycling.

5.6.3. UART and I2C Pin Assignment¶

Quick Summary

• UART and I2C functions can be mapped to arbitrary PA pins.
• Pin choices should still account for boot, wake, debug, production test, and board routing constraints.

Design Goal

Use flexible pin mapping to simplify routing without blocking required boot straps, wake pins, debug access, or production fixtures.

The SF32LB52x supports UART and I2C function mapping on arbitrary PA pins.

UART/I2C Checklist

• Pull-ups, voltage domains, and bus capacitance are correct for every I2C bus.
• UART pins needed for logs, download, or external modules are accessible.
• Pin multiplexing does not conflict with bootstrap, wake, display, storage, or debug functions.

5.6.4. GPTIM Pin Assignment¶

Quick Summary

• GPTIM functions can be mapped to arbitrary PA pins.
• Timer functions support PWM outputs, input capture, motor control, backlight control, and product-specific timing.

Design Goal

Reserve timer-capable functions early enough that PWM, capture, and timing features are not forced onto poor routing or wake-conflicting pins late in the design.

The SF32LB52x supports GPTIM function mapping on arbitrary PA pins.

GPTIM Checklist

• Timer channels required for PWM, capture, or control loops are listed in the pinout table.
• GPTIM pins do not conflict with backlight, motor, debug, or storage requirements.
• Bring-up plan includes checking PWM frequency, duty range, and pin polarity.

5.7. Manufacturing¶

5.7.1. Debug and Download Interface¶

Quick Summary

• PA18 and PA19 default to DBG_UART after power-up and are multiplexed with SWD.
• Reserve physical access to the debug/download pins on every prototype and production board.

Design Goal

Guarantee firmware download, debug logs, single-step debug, and failure recovery access even after the product enclosure and production fixture are defined.

The SF32LB52x supports a DBG_UART interface for download and debug, connected to a PC through a 3.3 V UART-to-USB dongle board. SWD and DBG_UART are multiplexed on PA18 and PA19; the default power-on configuration is DBG_UART, which supports single-step debugging as well as log output.

For DBG_UART single-step debugging and log output, consult the SFtool and Impeller manuals.

Debug Checklist

• PA18/PA19, ground, and the required power reference are exposed on test pads or connector pins.
• Debug access remains available after enclosure, battery, and display assembly.
• UART voltage level is 3.3 V compatible with the selected adapter or fixture.
• Recovery path is documented for a board that cannot boot application firmware.

5.7.2. Production Flashing and Crystal Calibration¶

Quick Summary

• Production programming and crystal calibration require stable power, DBG_UART access, PA01, and the required power/ground test points.
• Fixture access should be designed before the PCB mechanical outline and enclosure are frozen.

Design Goal

Make every production board programmable, calibratable, and recoverable without manual soldering or product disassembly.

SiFli provides an offline downloader for production firmware flashing and crystal calibration. Reserve at least these test points in the hardware design: PVDD/VBAT, GND, AVDD33, DBG_UART_RXD, DBG_UART_TXD, and PA01. See the "Offline Downloader User Guide" document included in the development package for the detailed flashing and calibration process.

Production Checklist

• PVDD/VBAT, GND, AVDD33, DBG_UART_RXD, DBG_UART_TXD, and PA01 test points are reserved.
• Test pads are reachable by the intended fixture after mechanical assembly.
• Crystal calibration flow and pass/fail limits are defined with manufacturing.
• Programming, calibration, and functional-test records can be tied back to the board revision.

5.7.3. Schematic and PCB Drawing Checklists¶

Use the official schematic and PCB checklist published on SiFli's wiki as the formal release gate — see the Schematic Checklist for the complete, item-by-item version. The local checklists in this guide are intended to catch common engineering issues before the formal checklist review.

Release Checklist

• Schematic checklist, PCB checklist, AVL check, DRC report, and impedance report are complete.
• Evidence screenshots are archived for power, clock, RF, display, storage, audio, USB, SDIO, DC/DC, and production-test access.
• Variant-specific assumptions are documented in the review notes.
• Open hardware risks are assigned to an owner before release.

Last updated: 2026-10-21