SF32LB56x Hardware Design Guide — Schematic Design Guidelines¶

5. Schematic Design Guidelines¶

5.1. Power System¶

Review processor rails, required local capacitors, PMIC output assignments, reset timing, and charger wiring together. The U and V variants share the same power-design method, but their power-pin names and load assignments differ.

Without power-path management, the system is connected directly to VBAT with the battery. This is lower cost, but downstream circuitry cannot be fully disconnected from the battery, increasing leakage and preventing the low-power Shipping Mode target. When the battery is over-discharged, charger trickle current must exceed the combined system and leakage load (i1+i2 in the source diagram). While the system is running, constant-current charge current must also exceed i1+i2; otherwise, the system load draws part of the charge current and the battery may not reach full charge. A power-path charger separates system power at VSYS from battery charging at VBAT, supports Shipping Mode, and can power the system from VSYS even when the battery is over-discharged.

For the U variant, choose among three power topologies according to peripheral I/O voltage and the system power target. In all three, AVDD33_ANA and AVDD33_AUD are supplied at 3.3V. The lowest-power topology supplies PVDD and VDDIO1–VDDIO4 at 1.8V and uses peripherals with 1.8V I/O. The intermediate topology keeps PVDD and VDDIO1 at 1.8V while supplying VDDIO2–VDDIO4 and peripheral I/O at 3.3V. The highest-power topology keeps only VDDIO1, which supplies the co-packaged PSRAM, at 1.8V; PVDD, VDDIO2–VDDIO4, and peripheral I/O use 3.3V. Use load switches for dynamic power management of external modules and keep them off by default when unused. For modules that must remain on, select devices with low quiescent current. The load-switch control GPIO's hardware default level must match the switch enable polarity so the switch remains off at startup; SiFli recommends a 1MΩ pull-up or pull-down at the enable input.

The U-variant PMU completes power-on reset when PVDD rises to 1.5V. A falling PVDD triggers brownout reset at the configured BOR threshold, which is configurable from 1.5V to 2.5V.

5.2. Operating Modes and Wake Sources¶

Operating mode, wake source, pull-up rail, and leakage-current decisions should be reviewed as one topic. Use wake-capable pins for buttons, touch, sensor interrupts, charger events, and other low-power wake signals.

BOOT_MODE selects startup behavior: high enters download mode; low makes ROM check for a user program, starting it if present and otherwise entering download mode. The U-variant Mode pin has an internal pull-down, may be left floating when unused, and shares the VDDIO2 domain. The V-variant Mode pin shares VDDIOA and should be held stable with a 10kΩ pull-up or pull-down; do not leave it floating or allow it to toggle from interference. Reserve a Mode test point on production boards; a jumper is useful on development boards for recovery.

Account for memory I/O power in low-power shutdown designs. In U-variant Standby, GPIO levels are retained and VDDIO1 can remain powered; put storage on MPI1/MPI2 into its low-power mode. In Hibernate, GPIO levels are not retained, so turn off VDDIO1 to prevent leakage through the co-packaged memory I/O. For the V variant, keep the co-packaged-memory I/O powered in Standby; before Hibernate, turn off VDDIOSA and VDDIOSB under PBR0 control and place NOR Flash in Deep Power-Down. VDDIOSC must remain powered.

5.3. Clock Generation¶

Keep the 48 MHz and 32.768 kHz crystals close to the chip, reserve matching capacitors, and protect crystal traces from BUCK, RF, display, motor, and charger noise.

5.4. RF¶

For both SF32LB56xU and SF32LB56xV designs, route the RF path as a 50-ohm controlled-impedance trace. If the selected antenna is already matched, no additional RF components are normally required, but the design should still reserve a π-type matching network for spurious filtering and final antenna tuning.

Place the RF matching network close to the chip side, not the antenna side. Keep AVDD_BRF filtering close to the chip pin, connect capacitor grounds directly to the main ground, route RF on the surface layer where practical, avoid vias and sharp corners, add dense ground shielding vias along both sides of the RF trace, and keep DC-DC, VBAT, crystal, high-speed clock, I2C, SPI, SDIO, I2S, and UART signals out of the RF area.

5.5. Display, Touch, and Backlight Interfaces¶

Display interface selection is a package-level decision. The U variant documents SPI/QSPI and JDI display options; the V variant also documents MCU8080 and DPI options. Touch interrupt, reset, and backlight controls should be assigned with wake and production access in mind.

5.6. Storage, Sensors, Audio, and Connectivity¶

Storage and display buses should not be assigned independently because both consume high-value GPIO groups and can drive PCB stack-up decisions. Confirm boot storage type, pull-ups, voltage domain, power-switch behavior, and fixture access before schematic freeze.

Match the storage I/O supply to the attached memory's logic level: U-variant storage I/O uses VDDIO3, while V-variant storage I/O uses VDDIOA2. Pull the SPI NAND Flash Hold# pin up to its supply through a 10kΩ resistor. SD1/eMMC is available on the V variant; do not apply the V-variant SD1/eMMC pin table to the U variant, which uses the SD2 storage interface.

For an external differential analog microphone, place at least 2.2µF DC-blocking capacitors in the ADC inputs and power the microphone from MIC_BIAS. The U-variant MEMS-microphone reference feeds MIC_BIAS through 1kΩ with a 4.7µF bypass capacitor; its microphone-output reference also shows a 0.01µF coupling capacitor. The U-variant analog-PA reference uses 33nF input coupling capacitors, with the differential low-pass filter close to the chip. Route analog DAC outputs as a guarded differential pair; keep parasitic capacitance below 10pF and trace length below 2cm. The V variant also provides I2S; its reference I2S amplifier is configured over I2C3. Place audio supply/reference capacitors close to their pins and route analog audio away from switchers and high-speed digital signals.

Both variants provide PWM for vibration motors. The motor may be powered directly from VBAT if its startup current does not destabilize the system. When BSP_PM_FREQ_SCALING is defined as 1, HCPU frequency scaling changes PWM frequency on PA pins; use a PB pin for this case. PB32 is an active-high power/reset input; a long press of at least 10s triggers reset. The U-variant reference connects the key through 1kΩ from VDDIOB and adds a 10kΩ pull-down and 0.1µF capacitor to ground. The V-variant reference uses a 1kΩ series resistor from VDD_1V8 and a 10kΩ pull-down. Other buttons and rotary encoders require pull-ups; for a mechanical encoder that does not return to the off state after rotation, its pull-up rail must be switchable in standby to avoid leakage.

U provides PBR0–PBR2 and V provides PBR0–PBR3. PBR0 transitions low-to-high during startup and can control an external load switch; the other PBR pins default low. PBR pins can output in Standby and Hibernate and can carry LPTIM; all except PBR0 can output a 32kHz clock. PBR pins can also be configured as wake inputs, but the MCU cannot receive an interrupt from that input after wake. Prefer LCPU PB pins for sensor I2C, SPI, control, and interrupt-wake signals; sensor power can be switched as needed from an SF30147C LVSW or LDO output.

All U/V PA pins can be muxed to UART, I2C, or GPTIM. On U, PB32/PB33/PB34 and PBR0/PBR1/PBR2 are exceptions; on V, PB32–PB36 and PBR0–PBR3 are exceptions. Review these restrictions together with wake, button, and PBR assignments.

5.7. Manufacturing¶

Reserve debug/flashing access, production flashing mode, crystal calibration access, power measurement points, RF test access, and PMIC control visibility. Verify the fixture can power the board, force boot/download mode, communicate with the chip, and collect calibration data.

At minimum, reserve VBAT, GND, VDDIO2, Mode, SWDIO, SWCLK, UART4_RXD, UART4_TXD, and one of PB20/PB21/PB25 as U-variant test points. For V, use VDDIOB instead of VDDIO2; the other signals are the same. When connecting J-Link, set debugger power to external input so the target board powers the debugger. The production download and crystal-calibration fixture must be able to access these points.

Last updated: 2026-10-21