SF32LB55x Hardware Design Guide — PCB Layout Guidelines¶

6. PCB Layout Guidelines¶

6.1. Footprint and Stack-Up¶

Use the package drawing, land-pattern requirements, and assembly capability of the selected QFN or BGA package. BGA packages require early confirmation of ball escape, via strategy, solder-mask rules, and fabrication limits.

6.1.1. Stack-Up and Fabrication Reference¶

SiFli recommends a conventional PTH process and a four-layer board for QFN68L and BGA145. For BGA169, the reference recommends one-step HDI with blind/buried vias. The illustrated four- and six-layer stack-ups have a finished thickness of 0.7 mm ±10%. These are reference constructions, not universal limits; confirm the selected package drawing, finished thickness, and process capability with the board fabricator.

The source figure specifies a finished board thickness of 0.7 mm ±10%, including plating and solder mask. It prints the L1/L4 copper-plus-plating thickness as 0.048 mil (0.001219 mm) and the L2/L3 copper thickness as 0.07 mil (0.001778 mm). These values differ markedly from customary PCB copper-thickness notation. They are transcribed as printed, not fabrication targets; obtain written confirmation from SiFli and the board fabricator before using them.

The source figure specifies a finished six-layer HDI board thickness of 0.7 mm ±10%, including plating and solder mask. The stack-up, dielectric parameters, and theoretical thickness are references; have the board fabricator verify them against the actual materials, copper weights, and impedance requirements.

6.1.2. Land-Pattern Dimensions¶

• BGA145/BGA169: 0.25 mm ball diameter and 0.5 mm pitch; the reference land pattern shows a 0.33 mm solder-mask opening and a 0.25 mm paste opening.
• QFN68L: perimeter pads are 0.2 × 0.55 mm on 0.35 mm pitch; the reference shows a 0.3 × 0.65 mm solder-mask opening and a 0.2 × 0.55 mm paste opening. The exposed pad is 5.49 mm square nominally, with a 5.39–5.59 mm range.

Check the package drawing and assembly house's stencil and solder-mask rules before releasing the footprint.

6.2. General PCB Rules¶

• Keep BUCK loops short and wide, with return current close to the switching loop.
• Keep RF, crystal, GPADC, and audio regions away from switching supplies, display clocks, motors, and chargers.
• Route high-speed memory and display interfaces over continuous reference ground.
• Place ESD protection close to connectors and route signals through the protection device first.
• Provide enough test points for power, boot, debug, RF, and production calibration.

6.2.1. Fabrication Clearances¶

The following values are transcribed from SiFli's PTH and six-layer HDI reference-rule figures. They are not substitutes for the fabricator's current rules for the selected stack-up.

In each source figure's same-net matrix, only selected cells are marked 0 mm; blank cells are unspecified. Do not infer that unlisted combinations also permit 0 mm clearance. Confirm every rule with the PCB fabricator before layout release.

6.2.2. Power and Ground Layout¶

• Place DC-DC inductors and capacitors close to their pins. Keep BUCK_VSW short and wide, minimize loop area, connect output-capacitor grounds to the plane with multiple vias, and make the BUCK_VOUT feedback trace wider than 0.25 mm. Do not place surface copper or unrelated traces beneath an inductor; use a solid ground plane on the adjacent layer.
• Place PVDD_PMU1 (pin 67) capacitors close to the pin and use a trace at least 0.3 mm wide. Place LDO/IO capacitors close to their corresponding pins; size traces for load current and keep them short and wide where ripple or stability is sensitive.
• Connect the QFN exposed pad directly to main ground with multiple vias, especially near RF and PMU regions. For BGA145 and BGA169, connect RF ground balls C12, C13, D12, and E13 to main ground as shown in the BGA145 ball map, BGA169 device 1 ball map, and BGA169 device 2 ball map. D2 and B3 are PMU ground balls on BGA169; on BGA145, D2 is PA79 and B3 is BUCK2_VOUT. Do not bridge separate ground balls together with surface copper.

Source-map clarification: The source prose repeats E13 in its RF-ground ball list. The RF-ground figure labels AVSS_TRF at C13, AVSS_RRF at E13, AVSS_BB at C12, and AVSS_VCO at D12. The coordinates above follow the figure; verify them against the ball map for the selected package before routing.

6.2.3. EMI, ESD, and Protection¶

Keep clocks and noisy power routes on inner layers where practical. Place ESD devices at the connector so each signal passes through the device before entering the board, without a branch stub; use a short, wide ground path with a direct via to the plane. For USB charging, place the test point on the connector side of the TVS. For the battery input, place the TVS between the connector and board load so the path to the chip passes the TVS first, and keep its ground connection short.

6.3. Interface Routing¶

Clock traces should be short, shielded, and isolated from fast digital signals. RF should be controlled as a 50 ohm path with a compact matching network. Storage and display traces should be length-controlled according to their speed and routed as grouped buses. Audio and GPADC signals should be shielded and kept away from switching currents.

6.3.1. Crystal Placement and Routing¶

• Place each crystal inside the shielded area, more than 1 mm from the board edge and more than 5 mm from heat sources such as the PA, charger, and PMU. Keep at least 0.25 mm clearance around the crystal.
• Route the 48 MHz crystal traces on the top layer; keep them 3–10 mm long and 0.1 mm wide. Keep 48M_XI and 48M_XO at least 0.15 mm apart, as shown in the source routing model, and provide three-dimensional ground shielding. Keep the routes away from VBAT, DC-DC, and high-speed signals. The source prose calls for a copper keep-out on the top and adjacent layers beneath the crystal region and prohibits unrelated routing through that region.
• Route the 32.768 kHz crystal traces on the top layer; keep them no longer than 10 mm and 0.1 mm wide. Keep XI and XO at least 0.15 mm apart and provide three-dimensional ground shielding. The source prose calls for a copper keep-out on the top and adjacent layers beneath the crystal region and prohibits unrelated routing through that region.

6.3.2. RF and High-Speed Interfaces¶

Place the RF matching network close to the chip, not at the antenna. Keep the AVDD_BRF capacitor close to its pin and connect its ground directly to main ground. Route RF on the top layer without layer changes, with a 50 Ω controlled impedance. The source prose recommends a width greater than 10 mil, while the source checklist marks ≥10 mil as Required; preserve that distinction and size the final trace for 50 Ω on the selected stack-up. Use three-dimensional ground shielding and stitching vias on both sides; avoid sharp corners and keep DC-DC, VBAT, clocks, and high-speed I2C/SPI/SDIO/I2S/UART away from the RF region.

Route MIPI_DSI as 100 Ω differential pairs and length-match data pairs to the clock pair. Length-match OPI PSRAM and LCDC SPI/QSPI buses. Guard clock and I2C routes with ground where practical and avoid long parallel runs with unrelated signals.

6.3.3. Analog Routing¶

Surround GPADC routes with ground shielding in three dimensions and keep them away from noisy battery-voltage and temperature-sensing paths. Review divider impedance and leakage against the required settling time.

6.4. PCB Layout Checklist¶

Each table below covers one PCB layout review area. When an Applies To column is not present, the row applies to all variants covered by the workbook.

6.4.1. Package¶

6.4.2. Power Supply¶

6.4.3. Power Supply Capacitor and Inductor Placement¶

6.4.4. Clock¶

Source clarification: The source prose calls for a copper keep-out on the top and adjacent layers beneath the crystal region; the checklist names the top layer for a 4-layer board and layers 2 and 3 where required. The 48 MHz routing model and 32.768 kHz routing model both depict an L2 ground plane beneath the XI/XO routes. The source does not clarify whether the keep-out applies only beneath the crystal package or also beneath the routing, nor how the layer requirements correspond. Confirm the required keep-out with SiFli before release; do not infer it.

6.4.5. Buttons¶

6.4.6. RF¶

6.4.7. High-speed Signals¶

6.4.8. ADC¶

6.4.9. Test Points¶

6.4.10. Ground¶

Last updated: 2026-10-10