SF32LB57x Hardware Design Guide — Storage & Manufacturing¶

5.6. Storage and Connectivity¶

5.6.1. Storage and Boot¶

Storage and boot decisions must be reviewed together. The selected boot medium determines strap resistors, default storage power state, bus allocation, and production recovery access.

Parts with package-integrated SPI NOR Flash boot from it by default. Parts without package-integrated SPI NOR Flash must boot from external storage. The external boot medium is selected by PA13 (Bootstrap[1]) and PA17 (Bootstrap[0]). The source schematic shows a jumper and a 7.5 kΩ pull-up position on each pin, tied to VDD33_VOUT1/VDDIOA.

5.6.2. Storage Interfaces¶

SF32LB57x supports external SPI NOR Flash, SPI NAND Flash, SD NAND Flash, and eMMC. Only MPI3 on PA12 to PA17 supports SPI NOR and SPI NAND; either SDIO interface can connect to SD NAND or eMMC. Package-integrated memory on some orderable parts occupies MPI3.

Before schematic freeze, confirm:

• Whether package-integrated Flash or PSRAM occupies an MPI channel.
• Which supported external boot medium is used: SPI NOR, SPI NAND, SD NAND, or eMMC.
• Whether IO voltage matches the storage device.
• Whether pull-ups, chip select, clock, data lines, and power control satisfy boot requirements.
• Whether the external boot medium has the correct default power state.

5.6.3. Boot and Power Control¶

An eMMC device has separate VCC and VCCQ power domains. Switching both rails together reduces shutdown power, but eMMC resumes from sleep more slowly and average CPU power is higher. Switching only VCC while keeping VCCQ on increases shutdown power, but eMMC resumes faster and average CPU power is lower.

“Not specified in source” means the source checklist gives no requirement for that cell; it does not imply that a pull-up is unnecessary.

The external boot selection is shown in Table 5.6-1 and Figure 5.6-1. The storage power-switch enable is fixed to PA21 and is active high. Choose the storage supply according to the power-supply variant:

• Battery-powered variants: external SPI NOR Flash may be powered continuously from VDD33_VOUT1; SPI NAND Flash must be powered through a switch after VDD33_VOUT1; SD NAND Flash and eMMC use an external LDO, preferably enabled by PA21. A package variant without PA21 may use a GPIO whose reset default is pull-up.
• 3.3 V-powered variants: all external boot storage uses an external LDO; PA21 is the recommended LDO-enable control.
• SPI NOR Flash may remain powered continuously; SPI NAND, SD NAND, and eMMC require a power switch. For boot from external media, its supply must be on by default at startup.
• Reserve pull-up footprints on PA13 and PA17; populate them for the selected boot medium. The recommended value is 7.5 kΩ. See Table 5.6-3 for the MPI3 pin-specific requirements.
• If package-integrated storage already occupies MPI3, external MPI3 usage is limited to SD NAND or eMMC; do not attach external SPI NOR/SPI NAND to that channel.
• Match the storage device's operating IO voltage to the MCU IO supply, and use a storage part listed on the project's Approved Vendor List (AVL).

5.6.4. GPIO and Pin Multiplexing¶

GPIO planning should happen before product peripherals are fully assigned, because boot, debug, wake, USB, analog, display, storage, and high-speed signals can constrain otherwise flexible matrix routing.

5.6.5. Pin Planning¶

SF32LB57x supports flexible pin multiplexing, but the following signals should be fixed early:

• RF, crystals, power, USB, analog audio, GPADC, boot, and debug pins.
• High-speed display, SDIO, storage, and DCMI interfaces that require specific pin groups.
• Wake GPIOs, boot configuration, SWD switching, and production-test pins.

5.6.6. GPIO Guidelines¶

• Configure unused GPIOs to a defined state.
• Match peripheral IO voltage with the corresponding IO supply domain.
• Include sleep leakage from GPIO pull-ups in the power budget.
• When a pin is reused as analog input, USB, audio, or a special function, configure digital input/output paths according to the user manual.
• Flexible matrix routing does not remove high-speed layout constraints. Respect pin group and PCB requirements.

Every GPIO can reach Function 0-15 through the IO MUX table below. The IO MUX table's Function 16-255 column points to matrix routing; the matrix table that follows enumerates function indices 16-175. Use both tables together to confirm exactly which physical pin a given peripheral signal can land on before freezing the schematic.

Bold marks the pin's function at reset. PUPD is the internal pull direction at reset (PU pull-up, PD pull-down, - none). # marks an analog function.

Any GPIO can be matrix-mapped to any of the functions above (subject to the routing and layout constraints noted elsewhere in this guide); the index and sub-index columns are the exact register field values used when configuring the matrix router in firmware.

5.6.7. General Interfaces¶

Apply the same review pattern to every general-purpose interface: electrical connection, IO voltage, reset/sleep default state, pull-up rail, ESD exposure, and conflicts with boot, debug, wake, or high-speed functions.

PA34 supports the power key and long-press reset. Reset is active high, so fit a 10 kΩ pull-down on the main board; pressing the key drives the pin high, and a 10-second long press triggers hardware reset. The GPADC resistor-ladder reference circuit uses 1.1 kΩ, 2.8 kΩ, and 5.1 kΩ key resistors. Its node labels are 2.97 V/1.62 V, 2.58 V/1.41 V, and 2.19 V/1.19 V, respectively. The PA34 node also has a 10 kΩ pull-down and a 100 nF capacitor to ground. Add ESD protection near every exposed key.

5.6.8. Interface Review Principles¶

Review four items for every peripheral interface:

1. Electrical connectivity, including crossed signals, pull-up/down resistors, ESD, and termination.
2. IO voltage-domain compatibility, including back-power risk when the peripheral is off.
3. Safe reset and sleep default states.
4. Conflicts with boot, download, SWD, USB, wake, or high-speed display multiplexed functions.

5.6.9. UART¶

• SF32LB57x provides three full-duplex UARTs with baud rates up to 6 Mbps and configurable data formats. UART signals can use Function 0-15 pins or be matrix-routed to any GPIO.
• MCU RXD connects to peripheral TXD; MCU TXD connects to peripheral RXD.
• Match peripheral IO voltage with the MCU IO domain.
• Review reset-state behavior for UART pins that are multiplexed with USB, boot, download, or debug functions.
• PA18 and PA19 are the default DBG-UART pins. For UART test interfaces that are frequently plugged and unplugged, the source recommends PA18, PA19, PA43, or PA44; this GPIO group is rated to 5.5 V. For long test leads, add a 100 Ω series resistor to suppress overshoot.

5.6.10. I2C¶

• SDA and SCL require pull-up resistors.
• SF32LB57x provides four I2C interfaces, each supporting host and device modes; matrix routing can assign them to any GPIO.
• The source recommends 4.7 kΩ for Standard-mode (100 kHz), 2.2 kΩ to 3.3 kΩ for Fast-mode (400 kHz), and 1 kΩ to 2.2 kΩ for Fast-mode Plus (1 MHz). For 400 kHz, 2.2 kΩ is a starting point; adjust for bus capacitance.
• One pull-up set near the host is sufficient for a shared I2C bus; do not add a separate set at every device. Power the pull-ups from the peripheral rail so they turn off with it and do not cause sleep leakage.
• Ensure every device on the same bus has a unique address.

5.6.11. SPI¶

• SF32LB57x provides two SPI interfaces, each supporting host and device modes. They can use Function 0-15 pins or matrix routing.
• MCU SDO connects to peripheral SDI; MCU SDI connects to peripheral SDO.
• Match CLK, CS, mode, phase, polarity, and maximum frequency to the peripheral datasheet.
• Keep high-speed SPI routing short with a continuous reference ground. Add series damping if signal-integrity testing shows it is needed.
• SPI below 30 MHz may use matrix routing to any GPIO; above 30 MHz, prefer dedicated Function 0 to Function 15 pins.
• For high-speed SPI, place a 22 ohm to 27 ohm series resistor near the driver and reserve a shunt capacitor footprint on the clock line for signal-integrity tuning.

5.6.12. SDIO¶

• SF32LB57x has two SD/MMC host controllers; they operate only as hosts and can connect to SD cards, SDIO peripherals, and eMMC. SDIO signals are fixed to their pin-mux GPIO assignments.
• Route SDIO signals as a group.
• Keep total length within about 50 mm and group skew within about 6 mm where practical.
• Keep CLK, CMD, and DATA traces over a continuous reference ground.
• Verify pull-ups, power control, and voltage domains for SDIO/eMMC/SD NAND.
• At 24 MHz, the internal GPIO pull-ups may be sufficient for CMD and Data0 to Data3; at 48 MHz and above, add 10 kohm external pull-ups on CMD and Data0 to Data3.
• Add 27 ohm to 33 ohm series resistors on SDIO signals and reserve a shunt capacitor footprint on the clock line.
• For an external TF-card socket, pull the card-detect DET pin up to 3.3 V through 10 kΩ and configure its MCU pin as an internal pull-up input. Add ESD protection to both the SDIO signals and the power path.

5.6.13. USB¶

• Route USB DP/DN as a 90 ohm differential pair.
• USB DP/DM commonly use PA35 / PA36 multiplexed functions. When USB is enabled, ensure external circuitry does not force unsafe levels during reset.
• Place ESD close to the connector; route signals through ESD before the chip.
• Avoid stubs and maintain pair matching and reference ground continuity.
• If USB insertion must wake the device during sleep, connect a VBUS resistor divider to a hardware-wake GPIO; sharing that GPIO with charger-insertion detection is recommended.
• PA35 is fixed as USB_DP, and PA36 is fixed as USB_DM; these functions are not remappable. USB2.0 FS supports up to 12 Mbps.
• Reserve 22 ohm or 33 ohm series resistors near the chip side on DP/DM, plus unpopulated shunt capacitor footprints for signal-integrity tuning.
• The USB interface uses 3.3 V single-ended signaling. The chip has an integrated identification resistor; software can configure a 1.5 kΩ pull-up on DP or DM to identify a full-speed or low-speed device. Configure PA35 and PA36 as high-impedance inputs when enabling USB to avoid pin-mux conflicts.

5.6.14. CAN¶

• The chip provides two CAN interfaces compatible with CAN 2.0B; matrix routing can assign them to any GPIO.
• Match CAN transceiver supply and IO voltage to the MCU.
• Add termination, common-mode choke, and ESD according to system requirements.
• For industrial or vehicle environments, review surge, EFT, ESD, and ground-potential differences.

5.6.15. GPADC¶

• Keep GPADC input voltage within the 0 V to 3.3 V rated range.
• Only PA28 to PA38 (11 pins) are GPADC-capable through the pinmux; do not assign the function to other pins.
• Use 1% resistors for divider-based measurement.
• Place a 100 nF (0.1 uF) filtering capacitor close to the chip pin on every GPADC input.
• Keep GPADC traces away from DC/DC, RF, USB, SDIO, display clocks, and charging loops.

5.7. Manufacturing¶

5.7.1. Production Boot and Download Modes¶

Keep the default debug/download pins accessible to the production fixture, and reserve boot-mode controls before product IO assignment. The source checklist requires solderable test points on PA43 / PA44; it also calls for a pull-up and test point on PA00, with a resistor and test point on PA01 optional.

5.7.2. Production Programming and Calibration¶

The source calls for an offline programmer to program flash and perform crystal calibration. It does not specify RF calibration or supply-current testing in this section. Follow the source's probe dimensions, spacing, and orientation requirements when laying out production pads, and confirm the differing test-point lists in Table 5.7-3 with the production fixture owner.

See the SiFli offline programmer documentation.

Last updated: 2026-10-21