SF32LB58x Hardware Design Guide — Design Review Checklist and References¶

7. Design Review Checklist¶

• Confirm that the selected model's co-packaged Flash/PSRAM combination meets the product requirements
• Verify that the PMU supply (PVDD1/PVDD2/BUCK/LDO) and all other power-pin voltages are within the datasheet limits
• Verify that the selected BUCK inductor has a nominal inductance of 4.7 µH, DCR ≤ 0.4 Ω, and Isat ≥ 500 mA
• Confirm that the 48 MHz and 32.768 kHz crystals meet the recommended specifications and that their routing and keep-out zones meet the design requirements
• Verify a 50 Ω controlled-impedance RF trace and place the matching network close to the chip
• Confirm that the selected external storage interface is compatible with the intended boot design. Separately verify that the Mode pin is strapped high for download mode or low for user-application startup, as intended
• Confirm that display-interface routing (MIPI-DSI/SPI-QSPI/MCU8080/DPI/JDI) meets each interface's impedance and length-matching rules; for DSI, verify 100 Ω differential impedance, intra-pair length mismatch ≤0.5 mm, and inter-pair length mismatch ≤2 mm
• Confirm that USB routing meets the 90 Ω differential-impedance requirement. Route SDIO signals together, keep total routing length ≤50 mm, and limit within-group length mismatch to ≤6 mm
• Preserve SWD access and the selected debug-output interface from the six available UARTs, along with its signal pins and production test points
• Confirm that BGA pad vias are centered and the ground plane beneath the chip is continuous
• Verify key component part numbers against the latest SiFli Approved Vendor List
• Include stack-up and process-capability data, impedance and DRC results, the AVL, and focused layout screenshots in the review evidence pack
• Close all open schematic, layout, and manufacturing issues before prototype release, or explicitly track them to closure

8. Related Documents and References¶

Use the latest official documents when checking electrical limits, package data, pin multiplexing, software configuration, and component qualification.

Together, the Schematic Checklist (Section 5.8) and PCB Layout Checklist (Section 6.18) reproduce the applicable schematic and PCB items from the SF32LB58x Schematic & PCB Checklist workbook (V1.0, 2026-01-21), alongside the design guidance they check against.

9. Appendices¶

The appendices collect application and reference-design context. Use them as review aids after the main schematic and PCB rules in Sections 5 and 6 have been applied.

9.1. Appendix A. A Typical Smart Wearable or Smart Terminal¶

A typical SF32LB58x design for a wearable device or smart terminal includes the MCU, PMIC, high-resolution display, touch controller, boot storage, external memory or eMMC, sensors, vibration motor, audio input/output, Bluetooth antenna, crystals, USB, debug access, and production test access. The BGA256 package and high-speed display/storage interfaces make HDI process selection part of the system architecture, not just a PCB-layout detail.

10. Revision History¶

10.1. Checklist Revision History¶

The item-by-item checklist in the Schematic Checklist and PCB Layout Checklist is versioned separately from the guide, following SiFli's own SF32LB58x Schematic & PCB Checklist workbook.

Last updated: 2026-10-10