SF32LB52x¶

Overview¶

SF32LB52x is SiFli's cost-optimized MCU family for entry-level smart wearables, compact graphical HMIs, Bluetooth peripherals, and other space-constrained AIoT products that still need integrated display, audio, storage, and wireless capability.

At the platform level, the family combines a 240 MHz Arm Cortex-M33 STAR-MC1¹ application core with a dedicated 24 MHz low-power Bluetooth controller core, enabling the chip to run a responsive UI and application stack while keeping Bluetooth connectivity and always-on workloads separate.

For product planning, the key variants in SiFli's chip model guide fall into two supply-oriented groups:

• SF32LB520/3/5/7: lithium-ion battery-powered variants with an integrated charger path
• 52B/D/E/G/J: external-supply variants, where 52B/E/G/J target standard 3.3V systems and 52D targets a special 1.8V ultra-low-power rail

These groups are not interchangeable at the board level. The battery-powered and external-supply families are not pin compatible with each other, and the 1.8 V 52D variant is electrically distinct from the 3.3 V 52B/E/G/J group even when their package layouts appear similar.

Applications¶

SF32LB52x is recommended for Bluetooth-centric products where cost, integration, and battery life are the primary design considerations, including:

• Entry-level smartwatches and fitness bands
• Bluetooth modules and wireless adapters
• Bluetooth audio accessories
• Smart sensors and wearable devices
• Electronic shelf labels and smart badges
• Portable label printers
• eBike and eScooter displays
• Basic LVGL-based HMI devices

Development Resources¶

Features and Specs¶

Compute and Memory¶

• Arm Cortex-M33 STAR-MC1 application core up to 240MHz, with DSP and MPU
• Dedicated Arm Cortex-M33 STAR-MC1 Bluetooth controller core at 24MHz
• 32 KB instruction cache + 16 KB data cache
• 512 KB application SRAM plus 64 KB Bluetooth-controller SRAM
• Variant-dependent co-packaged memory options ranging from 1MB QSPI-NOR to 16MB OPI-PSRAM

Graphics and Audio¶

• ePicasso 2.0 2D/2.5D graphics accelerator
• eZip 2.0 hardware decoder for lossless graphics compression
• Dedicated LCD controller supporting SPI/DSPI/QSPI, including e-paper SPI, plus 8080-8bit
• 1x 24-bit Audio ADC with 99 dB SNR
• 1x 24-bit Audio DAC with 109 dB SNR

Wireless Connectivity¶

• Dual-mode Bluetooth 5.3 (Classic Bluetooth and BLE)
• Maximum transmit power:
  • 19 dBm for BLE/BR
  • 13 dBm for BT/EDR2 and BT/EDR3
• Sensitivity: -100 dBm @ BLE/1Mbps
• Dedicated Arm Cortex-M33 STAR-MC1 Bluetooth-controller core with 64 KB SRAM @ 24 MHz
• Sleep current: 2 µA in the product brief; system-level standby current depends on the operating mode and board-level leakage

Security¶

• AES/HASH/CRC hardware accelerators
• TRNG
• PSA Certified Level 1

Peripherals and I/Os¶

• 3x UART
• 4x I2C
• 2x SPI
• 1x USB2.0 FS
• 1x I2S
• 1x PDM interface (up to two digital microphones)
• 1x SD3.0/SDIO3.0/eMMC
• 1x 12-bit general-purpose ADC
• Temperature sensor
• RTC and watchdog timers
• 44 or 45 GPIOs depending on variant family

Power Supply¶

• Battery-powered group: SF32LB520/3/5/7 — powered directly from a single-cell Li-ion/Li-Po battery and intended for designs that use the integrated charging-oriented power architecture.

• External-supply 3.3V group: 52B/E/G/J — intended for regulated external-supply systems and pin compatible with one another.

• External-supply 1.8V group: SF32LB52D — intended for special ultra-low-power 1.8V designs and not electrically interchangeable with the 3.3V parts.

The battery-powered and external-supply groups are independent silicon configurations and are not pin compatible across those supply families.

Family Variants¶

For the key variants listed in SiFli's chip model guide, the practical part-selection split is:

• SF32LB520/3/5/7: lithium-ion battery-powered group, pin compatible within the group
• 52B/E/G/J: standard 3.3V external-supply group, pin compatible within the group
• SF32LB52D: special 1.8V external-supply variant for ultra-low-power scenarios

If you are migrating between memory tiers, the nearest content-correspondence map is:

• 520 ↔ 52B
• 523 ↔ 52E, with 52D as the 1.8V counterpart
• 525 ↔ 52G
• 527 ↔ 52J

This table follows the key variants in SiFli's Chip Model Guide; it is not a complete ordering catalog. The linked external-supply datasheet also lists SF32LB52HUD6 (1.8 V, QFN68L, 128 Mb PSRAM), while the hardware guide uses the additional suffix patterns 52AUx6 and 52D/F/HUx6. The available sources do not provide a single, consistent variant table. Before design release, verify the ordering status, supply limits, memory interface, and I/O details of any such SKU in its current datasheet.

Integration Path¶

Use this sequence to turn an SF32LB52x shortlist into a validated design:

1. Prove the firmware path. Start with the SiFli SDK getting-started guide, then use the SiFli SDK workflow and examples to validate the required peripherals and Bluetooth behavior.
2. Choose the integration vehicle. Evaluate SF32LB52-MOD-1 when a ready-integrated RF module suits the product; otherwise select the closest SF32LB52 development board for early firmware and peripheral validation.
3. Design and review the hardware. Use the local hardware design guide — including its schematic and PCB layout checklists — before releasing the schematic or layout. Confirm the correct supply-family baseline: 520/3/5/7, 52B/E/G/J, or 52D.
4. Verify the authoritative source. Check the applicable datasheet and SiFli [hardware design guide for 520/3/5/7] or [hardware design guide for 52B/D/E/G/J] against the exact orderable part and package.

Frequently Asked Questions¶

What are the key specifications of SF32LB52x? SF32LB52x pairs an application CPU (Cortex-M33 @240 MHz) with a low-power core (Cortex-M33 @24/48 MHz, a dedicated Bluetooth controller), 576 KB of internal SRAM and dual-mode Bluetooth (BT Classic + BLE). Graphics: ePicasso 2.0 Lite. Package: QFN68 (7 × 7 mm). USB 2.0 FS. Family-level values; verify the exact part number's datasheet.

Which display interfaces does SF32LB52x support? SPI / DSPI / QSPI / 8080 / EPD / JDI. Availability varies by part number and package.

How much in-package memory does SF32LB52x offer? Up to 16 MB of in-package PSRAM and up to 4 MB of in-package NOR Flash, depending on the part number.

What supply voltage does SF32LB52x need? 3.2–4.7 V (520/3/5/7), 2.97–3.63 V (52B/E/G/J), 1.8 V (52D), depending on the variant. Confirm the exact range in the datasheet.

Where do I start a hardware design with SF32LB52x? Start with the SF32LB52x hardware design guide for schematic, power, clock/RF and PCB layout guidance, then use the schematic and layout checklists before releasing the board.

Related Products¶

Module¶

SF32LB52-MOD-1 combines the SF32LB525UC6, which has 8 MB of co-packaged OPI-PSRAM in the standard configuration, with an RF matching network. The module measures 27.9 × 18.0 × 3.1 mm and suits projects that need SF32LB52-class capability without taking on chip-level RF layout and validation.

Development Kits¶

• SF32LB52-DevKit-LCD is the main display-oriented bring-up board for the SF32LB52 module ecosystem, with QSPI and MCU/8080 LCD connectivity.
• SF32LB52-DevKit-Core-3p3 is the compact external-supply core board for quick firmware, GPIO, and low-power bring-up on 52B/52J-class parts.
• SF32LB52-DevKit-Nano is the smallest 52-series dev board, useful when the target product is size constrained.
• SF32LB52-DevKit-ULP is the low-power-oriented board path for battery-focused evaluation and compact product experiments.

Reference Products¶

Typical SF32LB52 designs include entry-level smartwatches, fitness bands, Bluetooth accessories, compact graphical controls, electronic shelf labels, smart badges, portable label printers, and cost-sensitive eBike or eScooter displays.

Last updated: 2026-10-21