SF32LB57-DevKit-LCD¶

Overview¶

SF32LB57-DevKit-LCD is a multimedia evaluation board built around SF32LB57-MOD-WD (apparently intended as a SiFli module product, with WD likely standing for Wi-Fi Dual-band; this naming interpretation is not officially confirmed), combining the SF32LB57x MCU with SDIO Wi-Fi, boot Flash and peripheral connections. Use it to develop a smart HMI, camera terminal, intercom or connected display, and to validate graphics, capture, audio and connectivity before designing a carrier board.

Board Resources¶

The source describes two STAR-MC1 performance cores at 240 MHz, rated together at 1968 CoreMark, plus 592 KB retention SRAM (512 KB HPSYS + 80 KB LPSYS). See SF32LB57x for the full multicore architecture. The module includes QSPI-NOR boot Flash, variant-dependent OPI-PSRAM, a 48 MHz MCU crystal and a 40 MHz Wi-Fi crystal. Confirm the module marking before selecting a memory configuration.

The source specifies a 3.3 V SF32LB57x variant and castellated pads for mounting the module on a carrier board. OPI-PSRAM is optional and depends on the exact module part number; it is not fitted in every configuration.

SiFli identifies the Wi-Fi device as AIC8800D40LS-N and describes a Wi-Fi/Bluetooth combo in places. Distinguish this from the SF32 MCU’s own Bluetooth capability; verify the fitted radio, RF-switch routing and SDK drivers rather than assuming a second usable Bluetooth path. The board has an IPEX-1 antenna connector and Wi-Fi power, wake and antenna-switch controls.

The original block diagram is a functional overview, not a wiring reference. It shows TF data lines D0–D3 and places WS2812B under the IO expander, whereas the text specifies 1-bit TF SDIO and direct MCU control of WS2812B on PA_11/PA_08 by board revision. Confirm these connections against the matching schematic and SDK pin configuration.

First Run¶

For the display baseline, prepare the board, a compatible 40-pin / 0.5 mm DPI-RGB panel, a data-capable USB cable and a Windows, Linux or macOS computer. Optional equipment includes an IPEX-1 antenna, a DVP camera, a MicroSD/TF card, an 8 Ω speaker and a J-Link or DAP-Link debugger. UART logging and native USB testing together require two data cables.

1. With power disconnected, check FPC pin 1, contact orientation and panel voltage, then connect the display to FPC1. Attach the antenna before wireless tests.
2. Connect the USB-to-UART Type-C port, not the native USB port, and select its COM port in SifliTrace or Impeller.
3. For download mode, fit the BOOT MODE jumper J1 before powering or resetting. Remove J1 and reset for normal startup and serial logs.
4. First establish a serial hello-world baseline, then test a solid-color screen and touch, if the panel provides it. Add camera, audio, storage and wireless individually before testing coexistence.

A factory-programmed board may show its default UI at power-on; that depends on the installed firmware and panel. A blank screen alone does not prove a download failure. Follow SiFli-SDK Getting Started for the toolchain, environment and flashing workflow.

SDK Build Targets¶

The current SDK build configuration lists the targets below. These are exact build identifiers, not proof that every SF32LB57-MOD-WD board fits every target: match memory, display, pin configuration and board revision against your SDK checkout. In particular, the board guide does not map its WD module revisions to these target names.

• sf32lb57-lcd_n16r16_dpi
• sf32lb57-lcd_n16r8_dpi
• sf32lb57-lcd_n16r16_qspi

After setting up the SDK environment, this is a hello-world build example only for hardware matching the N16R16 DPI configuration. A successful UART hello-world does not validate the display, camera or Wi-Fi drivers.

cd example/get-started/hello_world/rtt/project
scons --board=sf32lb57-lcd_n16r16_dpi -j8

Power and Debug¶

Either Type-C connector can supply 5 V. U4 (ETA3425D2G) generates the main VDD_3V3 rail; U7 (ETA3425D2G) generates WF_3V3, independently enabled by IOEX_WF_PWREN. The USB-to-UART bridge is CH343P; the other connector exposes USB 2.0 FS on PA35/PA36. For SWD, use PA_43 (SWCLK), PA_44 (SWDIO), 3.3 V target reference and common GND. Do not apply a debugger’s 5 V output to a 3.3 V pin.

The board SWD diagram identifies J3 pin 17 as 3.3 V, pin 18 as SWCLK, pin 19 as SWDIO and pin 20 as GND. These board-header numbers are not the pin numbers on the debugger adapter; follow signal names when connecting the two.

Display and Camera¶

FPC1 is a 40-pin / 0.5 mm FPC-05FB-40PH20 connector using the ALIENTEK RGB pin order. RGB888 is the default; RGB565/RGB666 can release data pins when the panel and firmware support them. FreeIO also permits adapted QSPI, MCU8080, EPD and JDI tests through this connector. These need the correct adapter, power arrangement and firmware; they are not native DSI connections.

The source requires a QFN80- or BGA112-based module for full-width, 24-bit RGB888 and describes ePicasso 3.0 as a 2D/2.5D graphics accelerator. FPC1 pin 1 carries 5 V for panel backlight or display-driver boost circuitry; it is not a 3.3 V GPIO. J3 pins 3 and 5 share the camera/touch configuration I2C bus on PA_23/PA_22.

FPC4 is a 24-pin / 0.5 mm DCMI DVP connector. The source lists GC032A, OV2640, OV5640 and OV3660; OV2640/OV5640 are the default baseline. Other modules may require camera-supply changes per schematic notes. Camera rails include DVDD_1V5, DVDD_2V8 and AVDD_2V8; match the sensor’s requirements, not just the connector. DVP data lines use jumper-selected pins shared with Wi-Fi SDIO or TF-card SDIO. The default configuration does not support simultaneous use of the conflicting functions.

The three camera rails use independent LDOs. The annotated front-view image labels the camera connector as 22P, but the source text and FPC4 table specify 24 pins. Use the 24-pin table as the documented reference and verify the actual connector and schematic before mating a camera. The source also gives an ambiguous reset assignment at FPC4 pin 6 (IOEX_DVP_PDN/RESET); confirm its wiring rather than assuming reset and power-down are independently controlled.

Shared Pins and Revision Checks¶

• PA35/PA36 appear on FPC1 and also serve native USB FS: do not use the conflicting panel connections and USB device function together.
• SWD on PA_43/PA_44 shares pins with display/camera functions. Keep a debug recovery path.
• WS2812B uses PA_11 on V1.0 and PA_08 on V1.1. The source also assigns PA_11 to BL_PWM; resolve this before driving the LED or backlight.
• J3 matches Raspberry Pi 40-pin power/ground positions, not a Raspberry Pi software environment or universal HAT compatibility. Check voltage, pinmux and shared signals before attaching expansion boards.

Audio, Buttons and IO Expansion¶

The source describes a 24-bit DAC playback path through U8 (NS4150B), a mono Class-D amplifier, to J7 (MX1.25-2P); its default speaker is 8 Ω. Two PDM microphones use MSM261DGT007 or the pin-compatible LMD4020T261-AC23. PA_56 is PDM clock and PA_55 is PDM data; IOEX_PDM_PWREN controls their power and IOEX_AU_PA_EN enables the amplifier. Verify the actual audio format, gain and speaker limits before product use.

S1–S3 share PA_34 / GPADC_CH6, with source nominal key voltages 2.97 V, 2.58 V and 2.19 V. S4 is active-low KEY_RSTN. U11 (AW9523BTOR) provides 16 IOs over I2C on PA_22 (SCL) and PA_23 (SDA). The table preserves the source’s listed initial states; verify reset behavior and firmware initialization on your board. P0_2/P0_3 are not specified in that source table.

Connector Reference¶

Sources and Next Steps¶

Use the SF32LB57x hardware design guide and Design for Production for a custom board. Refer to Graphics, Audio and Bluetooth for subsystem development.

• SiFli SF32LB57x Product Documents
• SiFli User Manual Downloads
• Original SF32LB57x Hardware Design Guide

The board source marks the SF32LB57x user manual as pending publication; check the download directory for current availability.

• Original Chinese Board Guide
• Source Markdown
• SDK Build Configuration
• Display Tools
• Impeller Flashing Tool
• SiFli Store

SiFli’s source directs sample and small-volume purchases to its store and volume enquiries to sales@sifli.com. It also mentions open-source sample applications and QQ group 674699679; confirm eligibility and current availability with SiFli. For project enquiries, contact μForge.io.

Last updated: 2026-11-03